This application claims the priority benefit of Taiwan application serial no. 91100556, filed Jan. 16, 2002.
1. Field of Invention
The present invention relates to a device and a method for testing a semiconductor device. More particularly, the present invention relates to a device for testing a mask read-only memory (Mask ROM) and a method for testing a Mask ROM with the testing device.
2. Description of Related Art
The Mask ROM is the simplest one in the family of the read-only memory (ROM). The Mask ROM can be divided into two types, which have different structures and different coding (programming) methods. To program one type of the Mask ROM, a coding mask is used to determine the connection relationships between a plurality of metal lines and a plurality of memory units. To program the other type of Mask ROM, a coding mask is used to selectively adjust the threshold voltages of the memory cells and thereby to set the logic states (0/1) of the memory cells. The Mask ROM product is suitable for mass production because when the data to be stored in a Mask ROM product is changed, only the coding mask needs to be modified in the whole process. It is even possible to fabricate a lot of semi-finished products in advance, thus when an order is received, the Mask ROM products can be programmed readily and then delivered to the clients to shorten the turn-around time (TAT) of the products.
After a Mask ROM process is finished, a testing procedure is usually performed to measure an array leakage of the Mask ROM, so as to determine if the Mask ROM device is qualified.
Refer to FIG. 1 and FIG. 2, wherein FIG. 1 illustrates a top view of a common Mask ROM and FIG. 2 schematically illustrates a cross-sectional view of the Mask ROM in FIG. 1 along the line I-Ixe2x80x2 and two array leakage paths therein.
As that shown in FIG. 1 and FIG. 2, the Mask ROM comprises a substrate 100, a plurality of buried bit-lines 102 in the substrate 100, and a plurality of word-lines 104 on the substrate 100 perpendicular to the buried bit-lines 102. Each word-line 104 has a gate oxide layer 103 formed thereunder. When the testing procedure is being performed, testing biases are applied to the Mask ROM to obtain a testing result. However, with the conventional testing method, only a total array leakage of the Mask ROM can be obtained and the major leakage path in the Mask ROM device can not be identified.
There are usually three possible leakage paths in a Mask ROM. Refer to FIG. 2, the first leakage path is the cell surface punch leakage represented by the arrow 10 and the second leakage path is the cell bulk punch leakage represented by the arrow 12. The third leakage path (not shown) is the bit-line to bit-line isolation leakage, which is the leakage occurring at the isolation parts between the end portions of the buried bit-lines 102 not covered by the word-lines 104.
However, with the conventional Mask ROM testing method, identifying the major leakage path out of the three possible leakage paths is impossible. Therefore, it is also impossible to exactly suit a remedy for the case to decrease the leakage.
Accordingly, this invention provides a testing device and a method for testing a Mask ROM to identify a major leakage path in the Mask ROM.
This invention also aims at eliminating the leakage source by suiting a remedy for the major leakage path identified.
The Mask ROM testing device of this invention comprises a substrate, a plurality of buried bit-lines in the substrate, and a plurality of word-lines on the substrate perpendicular to the buried bit-lines. Each word-line has a gate oxide layer formed thereunder and a spacer formed on the side-wall thereof Each buried bit-line has two end portions not covered by the word-lines with a combined length of about 3xcx9c30 xcexcm and the buried bit-lines can have an N-type conductivity or a P-type conductivity.
In the Mask ROM testing method of this invention, the Mask ROM testing device of this invention mentioned above is used and testing biases are applied to the Mask ROM testing device to obtain the value of a total leakage.
With the Mask ROM testing device and the method for testing the Mask ROM with the Mask ROM testing device of this invention, the major leakage path of the Mask ROM can be identified, which is not accomplishable with the testing method in the prior art.
Since the major leakage path in a Mask ROM can be identified with this invention, it is possible to appropriately provide a remedy for the major leakage path identified to decrease the array leakage.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.